1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a method of patterning insulating sidewall spacers using a wet etch.
2. Description of the Related Art
One variant of a basic conventional field effect transistor consists of a gate electrode stack fabricated on a lightly doped semiconductor substrate. The gate electrode stack consists of a gate dielectric layer and a gate electrode. A source region and a drain region are formed in the substrate beneath the gate dielectric layer and separated laterally to define a channel region. The gate electrode is designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain. In many processes, the source/drain regions consist of a lightly doped drain (xe2x80x9cLDDxe2x80x9d) and an overlapping heavier doped region. The source/drain regions are electrically isolated laterally from adjacent conducting structures by isolation structures such as insulating trenches or field oxide regions.
The performance of field effect transistors is dramatically affected by drive current and channel transconductance. As a general rule, higher drive current and channel transconductance translate into more desirable device performance. Drive current may be enhanced by reducing the length of the channel, as drive current is inversely proportional to channel length. Both drive current and channel transconductance may be improved by reducing the resistance of the channel. Channel resistance may be reduced by decreasing doping level in the channel and by minimizing weak overlap conditions. Weak overlap occurs where the edges of the gate electrode and the drain are offset.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a conducting layer of aluminum or polysilicon is deposited on the gate oxide layer. The conducting layer is then anisotropically etched selectively to the gate oxide to define a gate electrode stacked on top of the gate oxide layer. Following formation of the gate electrode, a source and a drain are formed, usually by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
In conventional processes incorporating LDD structures, a first set of oxide spacers is fabricated adjacent to the gate electrode prior to the LDD implant. The purpose of the first set of spacers is to provide a slight offset between the implanted substrate region and the gate edge so that damage to the edges of the gate electrode and the gate oxide layer and the substrate at the gate oxide edges is minimized. The first set of spacers is fabricated by forming a conformal layer of oxide over the gate electrode by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) or thermal oxidation and performing a subsequent anisotropic etch to define the spacers. The deliberate offset between the LDD edges and the gate edges is subsequently reduced by annealing. The goal of the anneal is to both activate the LDD and to eliminate the weak overlap.
Many conventional processes have incorporated RCA cleaning processes following the plasma etch to define the spacers. Some of these RCA process have employed etch mixtures of ammonium hydroxide and peroxide. Some unintentional etching activity on oxide films has been observed.
Following the LDD implant, a second set of insulating spacers is formed in what is largely a repeat of the earlier process used to fabricate the first set of spacers. The second set of spacers mask the substrate so that the second source/drain implant establishes overlapping heavier doped regions with an offset from the gate edges. In addition, the second set of spacers inhibit hot carrier injection from the later-formed silicide films on the substrate.
There are disadvantages associated with conventional techniques for patterning spacers. First, there is the potential for non-optimal device performance due to weak overlap.
Both the first and second sets of spacers are fabricated so that the width of each spacer falls within a specified range. Subsequent anneals to activate the source/drain regions are then tailored in view of the anticipated spacer width range to provide enough lateral diffusion of dopants to eliminate weak overlap. Control of spacer width is currently provided by monitoring the thickness of the conformal oxide layer that is deposited or grown over the gate electrode, and by monitoring the anisotropic character of the spacer etch. However, the outcomes of the oxide deposition or growth steps and the subsequent plasma etch are dependent upon a myriad of parameters, and thus do not always yield predictable results. Accordingly, later anneals may not yield the desired amount of lateral diffusion of source/drain dopants, and weak overlap may result.
In addition to weak overlap, conventional spacer processing may yield less than optimal channel transconductance and drive current due to the establishment of a larger than desired channel length. The widths of the spacers, in conjunction with the width of the gate itself, determine the pre-anneal channel length, and thus relate directly to the channel transconductance and the ultimate switching speed of the device. Accordingly, conventional spacer processes are typically designed to yield a spacer with a width that falls within a desired range that corresponds to a desired speed range. If the width of the spacers following plasma etch is larger than anticipated, the ultimate channel length may be larger than desired and result in degraded transconductance, drive current and switching speed.
Subsequent source/drain anneals may be lengthened in an attempt to narrow the channel length. However, lengthening anneals may consume thermal budget and lead to degraded device performance, particularly in processes sensitive to dopant migration, such as those used to fabricate p-channel devices.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
In accordance with one aspect of the present invention, a method of fabricating a circuit device is provided that includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to solution of ammonium hydroxide, hydrogen peroxide and water for a preselected time and rinsing with deionized water.
In accordance with another aspect of the present invention, a method of faceting a circuit device is provided that includes forming a gate on a substrate and forming an oxide layer over the gate. The oxide layer is anisotropically etched to define a first oxide spacer and a second oxide spacer adjacent to the gate. The widths of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of ammonium hydroxide, hydrogen peroxide and water for a preselected time and rinsing with deionized water.
In accordance with another aspect of the present invention, a method of fabricating a circuit device is provided that includes forming a gate on a substrate and forming an oxide layer over the gate. The oxide layer is anisotropically etched to define a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of ammonium hydroxide, hydrogen peroxide and water for a preselected time and rinsing with deionized water. A third spacer is formed adjacent to the first spacer and a fourth spacer is formed adjacent to the second spacer. The widths of the gate and the first, second, third and fourth oxide spacers is measured. The widths of the third and fourth oxide spacers are trimmed if the width of the gate and the first, second, third and fourth oxide spacers exceeds a preselected maximum value by exposing the third and fourth oxide spacers to solution off ammonium hydroxide, hydrogen peroxide and water for a preselected time and rinsing with deionized water.